Study of EUV Nanostructures Using AFM With High-Aspect Ratio Tip (Purdue, Intel, Bruker)

This academic collaboration between Purdue, Intel, and Bruker addresses a narrow but increasingly relevant metrology challenge as EUV lithography pushes toward sub-3nm nodes. The finding that high-aspect ratio AFM tips produce measurement artifacts on 40nm pitch photoresist features matters because accurate metrology becomes the gating factor for yield optimization as feature sizes shrink below the physical limits of measurement tools themselves.

The investment angle here is indirect but worth tracking. Intel's participation signals ongoing process control bottlenecks at advanced nodes, where the company is already struggling to match TSMC's yield curves on Intel 18A. If AFM metrology—considered a gold standard for non-destructive 3D profiling—proves unreliable for the narrow features required at 18A and beyond, fabs face a choice: accept higher defect rates, slow throughput with more conservative process windows, or invest in alternative metrology solutions. None of these options help Intel's already compressed margins as it ramps foundry services.

The semiconductor equipment implications are modest but directional. Bruker's AFM business is a small fraction of its $3 billion revenue base, and this research doesn't invalidate the technology so much as highlight its physical limits. The paper suggests that even specialized high-aspect ratio tips experience stick-slip friction and bending when measuring EUV photoresist sidewalls, meaning the problem isn't solved by better tip design alone. This potentially creates an opening for competing metrology approaches—optical scatterometry, x-ray techniques, or hybrid methods—though none offer AFM's combination of resolution and non-destructiveness.

What's more significant is the broader context: EUV metrology challenges compound as the industry moves toward High-NA EUV systems. ASML's High-NA tools, now shipping to Intel and expected at TSMC in 2025, will pattern even tighter pitches where these measurement artifacts become more pronounced. The research identifies photoresist shrinkage under electron beam exposure as one confounding factor, which is particularly problematic since SEM-based metrology remains the primary inline measurement technique. If both AFM and SEM introduce systematic errors at these dimensions, process control becomes substantially harder.

For Intel specifically, this adds to a growing list of execution risks around 18A. The company has already acknowledged yield challenges and pushed some customer tape-outs. Metrology limitations don't cause yield problems directly, but they obscure root causes and slow the debug cycles that separate leading-edge processes from production-worthy ones. TSMC's metrology infrastructure advantage—built over decades of 5nm and 3nm production—becomes more valuable if fundamental measurement techniques hit physical walls.

The competitive dynamic favors incumbents with the most process data and the tightest feedback loops between metrology, lithography, and etch. Samsung and TSMC have years of High-NA preparation; Intel is compressing that timeline. Equipment suppliers like KLA and Applied Materials, which offer integrated metrology solutions, may benefit if fabs need to deploy multiple complementary techniques to achieve the measurement accuracy that AFM alone can't deliver at these dimensions.

This is process engineering in the weeds, not a market-moving catalyst. But it's another data point suggesting the path to sub-2nm manufacturing is narrowing, with implications for who can execute and what capital intensity looks like for leading-edge fabs.